Qualified for automotive applications
AEC-Q100 qualified with the following results: Device temperature grade 1: –40°C to +125°C ambient operating temperature Device HBM ESD classification level 3ADevice CDM ESD classification level C6
Functional Safety-CapableDocumentation available to aid functional safety system design: ISO1540-Q1, ISO1541-Q1
Isolated bidirectional, I2C compatible, communication
Supports up to 1-MHz operation
3-V to 5.5-V supply range
Open-drain outputs With 3.5-mA Side 1 and 35-mA Side 2 sink current capability
±50-kV/µs transient immunity (Typical)
Safety-related certifications: 4242-VPK isolation per DIN VDE V 0884-11:2017-01 2500-VRMS isolation for 1 minute per UL 1577 CSA approval per IEC 60950-1 and IEC 62368-1 end equipment standards CQC basic insulation per GB4943.1-2011The ISO1540-Q1 and ISO1541-Q1 devices are low-power, bidirectional isolators that are compatible with I2C interfaces. These devices have logic input and output buffers that are separated by Texas Instruments Capacitive Isolation technology using a silicon dioxide (SiO2) barrier. When used with isolated power supplies, these devices block high voltages, isolate grounds, and prevent noise currents from entering the local ground and interfering with or damaging sensitive circuitry.
This isolation technology provides for function, performance, size, and power consumption advantages when compared to optocouplers. The ISO1540-Q1 and ISO1541-Q1 devices enable a complete isolated I2C interface to be implemented within a small form factor.
The ISO1540-Q1 has two isolated bidirectional channels for clock and data lines while the ISO1541-Q1 has a bidirectional data and a unidirectional clock channel. The ISO1541-Q1 is useful in applications that have a single master while the ISO1540-Q1 is suitable for multi-master applications. For applications where clock stretching by the slave is possible, the ISO1540-Q1 device should be used.
Isolated bidirectional communication is accomplished within these devices by offsetting the low-level output voltage on side 1 to a value greater than the high-level input voltage on side 1, thus preventing an internal logic latch that otherwise would occur with standard digital isolators.